An improved version of the classic 4-bit TD4-CPU. It uses less than 20 logic gate chips to build the world's simplest yet Turing-complete CP
Designed by Denjhang's Retro Hardware in China
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What is it? An improved version of the classic 4-bit TD4-CPU. It uses less than 20 logic gate chips to build the world's simplest yet Turing-complete CPU. Using 16*4 capacity ROM, manual programming,…
Read More…An improved version of the classic 4-bit TD4-CPU. It uses less than 20 logic gate chips to build the world's simplest yet Turing-complete CPU. Using 16*4 capacity ROM, manual programming, no programmer required, plug-in and play, it is a good helper for cultivating hobbies and beginners learning assembly and computer composition.
The overall architecture is built around the A accumulator. There are two program status registers (CF, ZF) that support instructions such as idle running, addition and subtraction, comparison, transfer, input and output, and jump. There is a 4-bit input port and a 4-bit output port. Operating frequency 0-100Hz. The output port is a digital tube that can latch and display the 8421BCD code.
Richer register space: Compared with the original TD4-CPU, which has only two general-purpose registers, this design is modified to add a 164-bit register file to the ACC, and the register file is addressed by an additional pointer register.
Higher utilization ROM: The original TD4 uses fixed-length instructions, and instructions without immediate data also occupy the corresponding immediate data space, while MiniMax 4bit adds a variable-length instruction buffer that can automatically decode instructions; when the instruction length is 1 When 4, it is executed directly. When the instruction length is 2*4 (including immediate data), it is automatically recognized, buffered and then executed, which effectively improves the program memory utilization. Under any instruction combination, the ROM utilization is 100%. Therefore, although the DIP switch memory is reduced by half, the actual number of executable instructions is only reduced by about 25%.
Instructions: NOP, ADD, SUB, CMP, IN A, OUT A, MOV A,reg, MOV reg,A, MVI A imm, MVI P imm, JMP, JMZ, JMC, JNC.
The address space of the DIP switch ROM is 0x0-0xF. The first one from the left in the first row is 0x0, the second one from the left is 0x1...and so on. The fourth row from the left is the address. 0xF.
When executing a single-length instruction, you only need to program a 4-bit command. For example, to execute ADD, you only need to set the DIP switch at the address to 4'b0001, and the next instruction will start at the next address. When executing a double-length instruction with an immediate value, the address where the instruction needs to be placed is first placed in the upper 4 bits, and the lower 4 bits of the immediate value are placed at the next address. For example, if MVI A, 5 is executed and execution starts from address 0x4, then 0x4 4'b1000 is placed at the address, followed by 4'b0101 at address 0x5, and address 0x6 is the next instruction... Although the command can only be fetched once at a time during execution, which is one 4bit, the system detects that it is When using a double-length command, only execute the NOP when taking the first 4 bits, and remember what the command is. In the second cycle, take another 4 bits to form a complete double-length instruction, and then perform the corresponding operation.
Single 5V power supply, Type-C power interface.
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